Alice & Bob, the three-year old quantum computing French startup targeted on Cat qubits, and researchers from the National Institute for Research in Digital Science and Technology (Inria, France) right now reported a brand new quantum error correction structure – low-density parity-check (LDPC) codes on cat qubits – to scale back {hardware} necessities for helpful quantum computer systems.
“This new architecture using LDPC codes and cat qubits could run Shor’s algorithm with less than 100,000 physical qubits, a 200-fold improvement over competing approaches’ 20 million qubit requirement,” stated Théau Peronnin, CEO of Alice & Bob, within the official announcement. “Our approach makes quantum computers more realistic in terms of time, cost and energy consumption, demonstrating our continued commitment to advancing the path to impactful quantum computing with error corrected, logical qubits.”
The latest paper is a part of a gentle stream of latest error correction/mitigation analysis rising at the beginning of 2024 and is a hopeful harbinger for the remainder of the yr. IBM this month revealed work on a extra environment friendly implementation of magic state distillation for logical qubits. D-Wave lately introduced improved error mitigation on its annealing quantum Advantage2 structure.
“Over 90% of quantum computing value depends on strong error correction, which is currently many years away from meaningful computations,” stated Jean-François Bobier, companion and director on the Boston Consulting Group, within the official announcement. “By improving correction by an order of magnitude, Alice & Bob’s combined innovations could deliver industry-relevant logical qubits on hardware technology that is mature today.”
Alice & Bob say their latest theoretical work, available on arXiv (LDPC-cat codes for low-overhead quantum computing in 2D), advances earlier analysis on LDPC codes by enabling the implementation of gates in addition to using short-range connectivity on quantum chips. “The resulting reduction in overhead required for quantum error correction will allow the operation of 100 high-fidelity logical qubits (with an error rate of 10-8) with as little as 1,500 physical cat qubits,” says the corporate.
Cat qubits alone already allow logical qubit designs that require considerably fewer qubits, says the corporate, due to their inherent safety from bit flip errors. In a earlier paper by Alice & Bob and CEA, researchers demonstrated how it might be potential to run Shor’s algorithm with 350,000 cat qubits, a 60-fold enchancment over the state-of-the artwork.
Here’s the summary from recent paper (barely reformatted):
“Quantum low-density parity-check (qLDPC) codes are a promising development for drastically lowering the overhead of fault-tolerant quantum computing (FTQC) architectures. However, all the recognized {hardware} implementations of those codes require superior applied sciences, equivalent to long-range qubit connectivity, high-weight stabilizers, or multi-layered chip layouts. An various method to scale back the {hardware} overhead of fault-tolerance is to make use of bosonic cat qubits the place bit-flip errors are exponentially suppressed by design. In this work, we mix each approaches and suggest an structure primarily based on cat qubits concatenated in classical LDPC codes correcting for phase-flips. We discover that using such phase-flip LDPC codes gives two main benefits.
- “First, the {hardware} implementation of the code will be realised utilizing short-range qubit interactions in 2D and low-weight stabilizers, which makes it readily suitable with present superconducting circuit applied sciences.
- “Second, we show the way to implement a fault-tolerant common set of logical gates with a second layer of cat qubits whereas sustaining the native connectivity. We conduct a numerical brute power optimisation of those classical codes to search out those with the perfect encoding fee for algorithmically related code distances. We uncover that a number of the greatest codes profit from a mobile automaton construction. This permits us to outline households of codes with excessive encoding charges and distances.
- “Finally, we numerically assess the performance of our codes under circuit-level noise. Assuming a physical phase-flip error probability ϵ≈1%, our [165+8ℓ,34+2ℓ,22]code family allows to encode 100 logical qubits with a total logical error probability (including both logical phase-flip and bit-flip) per cycle and per logical qubit ϵL≤10−8 on a 758 cat qubit chip.”
Alice & Bob observe that “in previously proposed qLDPC codes implementation, most notably IBM’s last year’s paper, long-range qubit connectivity and high-weight stabilizers were required, which represent a daunting technical challenge. In contrast, Alice & Bob’s combined approach of cat qubits with classical LDPC codes allows the use of short-range, local qubit interactions and low-weight stabilizers.”
This easier structure, contends Alice & Bob, allows for the primary time the implementation of a fault-tolerant set of parallelizable logical gates with out extra {hardware} complexity. Allowing for logical gates is a essential step for the implementation of quantum algorithms and practical quantum computing altogether.
An essential subsequent step, in fact, is to truly show the method on a bodily chip. Just final month, Alice & Bob introduced the tape out of a brand new chip – the 16-qubit quantum processing unit (QPU), Helium 1 – “expected to improve error rates with every qubit added, making it a prototype for the company’s first error-corrected, logical qubit.”
In the paper, the researchers write, “Thanks to the truth that we’re contemplating native codes in 2D, the bodily realization of the chip is vastly simplified in comparison with architectures that use high-encoding fee quantum LDPC codes for traditional qubits, which essentially require long-range connectivity. Here, the codes will be carried out and operated inside a single reminiscence layer, with native stabilizers of weight 4, that’s, with precisely the identical constraints because the floor code that has already been experimentally realized. Note that the locality of the codes alleviates the necessity for long-range couplers, that are technologically difficult to appreciate in large-scale architectures.
“To operate the architecture, as discussed in Section IV, it suffices to add a computing layer with repetition codes, which remains simpler than many existing proposals to realize gates on high-rate LDPC codes. A possible way to realize our two-layer architecture is to use flip-chip technology, inspired by semiconductors and successfully adapted to superconducting processors. The two layers are manufactured separately and then joined face-to-face using indium bump-bonds, where the indium establishes a superconducting galvanic connection between the two chips. Alternatively, the technology of TSV (through silicon vias) would also allow for the realization of our architecture (both sides of a chip are metallized and connectivity is established through the substrate). Figure 9 (see below) represents all qubits, including ancillary qubits and routing qubits, and the required connectivity to implement and operate the code (the qubits of the magic state factories of the computing layer are not shown).”
Link to launch,
